CAD and VLSI

synopsys acquires Magma

2011-12-01T13:10:00.000-08:00

This is big news in CAD circles. One of the top 4 EDA companies gets gobbled up by another. Foes that fought desperately over Lucas VG's patents (an innovator turned villain!) on super cell's are now going to sleep in the same bed and kiss and makeup (and discuss super/hyper cells probably!). Welcome to the dirty world of EDA.

Leakage is a pain..

2011-10-24T09:33:00.001-07:00

I am not sure of any existing tools which give an accurate estimate of active state leakage. We can evaluate leakage in the typical and worst case Leakage corners (which gives us the lower and upper bounds). The problem gets exaggerated from the lower bound if the chip gets hotter than 25C. It is interesting to note that fabs have migrated to using HighK dielectrics in the sub 40nm processes.

Logic synthesis and the standard cell library...

2011-10-21T14:19:00.000-07:00

It was the best of times, it was the worst of times, it was the age of wisdom, it was the age of foolishness, we had everything before us, we had nothing before us, we were all going direct to heaven" —The opening paragraph of A Tale of Two CitiesThese feelings arise when one takes a closer look at standard cell libraries and logic synthesis tools. while standard

Dennis Ritchie

2011-10-15T03:42:00.000-07:00

Computing as we know it today would be non existent without C and Unix, and yet so many people would be unaware of this genius who was found dead at his home at the age of 70.

Extreme Design Automation get acquired by Synopsys

2011-10-12T11:58:00.000-07:00

This is bad news for design community. We can only see the price of PT and PT-SI shoot through the roof now for lack of a good alternative (Tekton?). GoldTime was a decent timer correlating quite well with primetime SI and was within 2% of spice. I begin to Wonder if Synopsys will just kill the tool which has been a thorn in their flesh for the past few years!

Does global mode hold fixing make sense?

2009-10-16T15:31:00.001-07:00

Yes :-----1. It's supported in most CAD tools.2. Optimizations are still ongoing in the physical design flow. 3. A lot of hold buffers can be inserted in the data base quite easily before it is routed.4. This would reduce subsequent eco size post route and would enable quicker and easier converge on remaining hold violations and DRC.No:---1. A Huge number of Hold Buffers are added. This will

It's Raining Buffers!!

2008-02-29T06:24:00.000-08:00

Shrinking feature sizes->increasing die sizes->faster clocks->interconnect density->reducing supply voltages->Overbuffering? (courtesy: Henny Penny).well..I will trust henny penny and be his humble devotee. Will I end up with higher area and more power consuming silicon? The CAD guys will tell me that my buffer counts are realistic. Buffering under elmore delay model can be off by as much as 200%

Correlation issues in a typical CAD flow

2008-02-03T04:01:00.000-08:00

There can be numerous issues relating to correlation across various steps in a typical ASIC CAD flow. These issues can cause timing/area/power convergence problems in meeting ASIC tapeouts.1. Logic Synthesis:-------------------At logic synthesis step not much is known about wires in the design. Wires can be estimated using statistical models based on design size and cannot be computed. The delay

Design of a 50M gate ASIC..

2008-01-31T09:55:00.000-08:00

These are 10% of the problems ASIC designers face in Physical Design and STA of a 50M gate count ASIC. Some of the problems are:-------------------------1. Not many CAD tools exist out there which can handle this design flat atleast in an initial prototyping phase (synthesis + cluster placement) to arrive at the initial logical/physical hierarchies. 2. This leaves us with 50 partitions (assuming

on routing (Routing-2)..

2008-01-03T06:35:00.000-08:00

Within the physical design flow of a multi million gate ASIC, one of the most critical and notoriously difficult steps to perform is Routing.To tackle this problem, it has been split up into sub problems such as1. Global routing2. Track routing3. Detail routing.One of the most critical and initial steps is global routing. The quality of this routing solution has a direct impact on1. chip

2007-12-03T06:25:00.000-08:00

courtesy:www.phdcomics.com :)

Dreaming in code (This was an awesome interview by Peggy Aycinena)

2007-08-04T09:45:00.001-07:00

Read the full article at:http://www.aycinena.com/index2/template.html?index3/archive/dreaming%20in%20code

Other worries which will limit-> towards gridlessness. (Routing-1)

2007-07-28T08:16:00.000-07:00

To handle various cost functions and constraints of deep sub micron layouts, the router will need to have the capability to perform1. variable wire widths2. variable spacing requirements3. shielding/interleaving capabilities.These requirements lead towards gridlessness. When designing a detailed router utmost care needs to be taken so that interconnect parasitics after detailed route do not

Gridded and gridless routers (Routing-0)

2007-05-19T00:22:00.000-07:00

Interconnect optimization (routing) is crucial in minimizing delay, noise and optimizing reliability. Variable rules for deep submicron (width and spacing) make the job of a VLSI Router so much more difficult. It's about how effectively we use the available space for routing with such complex design rules for < 65nm technology nodes.Gridless routers are run time and memory intensive [when working

An interesting article on cell model creation for statistical timing analysis

2007-05-07T11:36:00.000-07:00

Meeting timing at the worst or best-case corner can be very challenging, lengthening design schedules and negatively impacting power consumption. With a large range of potential delay values, often with a difference of as much as 50 percent or more between the slow and fast process corners, it becomes harder to meet both setup times at the worst-case corner and hold times at the best-case corner.

The great STA/Formal verification vs Gate level simulation debate

2007-05-05T10:48:00.000-07:00

why the heck do we still do gate level simulations? Are they not run time/memory intensive? what is the confidence with which we can tapeout a chip without a gate level sim?here are some views on this topic from different industry veterans at deep chip.I didn't want to miss this interesting debate. Hence included it in the blog. This post is from John Cooley's deepchip.comhttp://www.deepchip.com/

Electrons caught in the act of tunneling..

2007-04-28T07:52:00.000-07:00

Here is a very interesting article on how electrons were captured when they were Tunneling through an atomic nucleus under the influence of laser (TUI- Tunneling under influence :)). The article is from Phys-org website.We have to climb a mountain in order to conquer it. In quantum physics there is a different way of conquering things, i.e going through them: objects can reach the opposite side

Dr. Stok calls for Prescriptive CAD

2007-04-28T07:15:00.000-07:00

Design rules are rules which layout tools/editors (Routers, DRC checkers) have to adhere to so that final layout which goes to the fab can be manufactured correctly. With 65 nm and below technologies the number of rules are too many, becoming difficult to code (run sets are becoming too big for DRC checkers!) and are unmanageable. DFM is partly responsible for more rules in < 65 nm technologies.

EDA is dead (EE-Times) ?

2007-03-18T19:17:00.000-07:00

Here is an interesting article from EE Times :)--------------------------------------------------------------------------------EDA is dead. Yes, it's still needed: We're not going to go back to designing chips with rubilith again. But the reality is that fewer and fewer chips are being designed, and most of the differentiation of a system is moving into the software. Even Gary Smith, the longtime

International work shop on Logic Synthesis

2007-03-18T07:30:00.000-07:00

IWLS 2007, a premier work shop on logic synthesis and related technologies will be held at Paradise point resort & spa, San Diego, California from May 30th to June 1st 2007. Visit for more information.www.iwls.org

1.1.2 Let's blame logic synthesis

2007-03-10T03:45:00.000-08:00

why does an Equivalence Checker (EC) abort?Because the left hand (EC) does not know what the right hand (logic synthesis) is doing. In a situation where Equivalence checking is not able to prove some of the compare points right or wrong, it has the tendency to create abort points.How deep is the rabbit hole?Equivalence checkers solve problems like BDD isomorphism and Boolean SATisfiability. They

1.1.1. The Art of Equivalence Checking

2007-03-09T23:08:00.000-08:00

Ever wonder why RTL to netlist verification is needed? why is the process of Equivalence Checking (EC) so hard? Read on.... :)Logic Synthesis as a process is prone to Bugs. There are too many transformations happening in logic synthesis which can alter the netlist in a wrong manner and make it infer functionality other than what was intended in the original RTL. These bugs are not intentional but

1.1. Formal Verification

2007-03-09T07:04:00.000-08:00

Verification is a Major bottleneck in design flow. It consumes upto 75% of the overall design cost and effort. This is why several (Formal) methods have been proposed in recent times as alternatives to classical simulation to speed up the process. We can split up Formal techniques into different categories like1. Equivalence checking (EC)2. Property Checking3. Symbolic simulationThe development/

1. VERIFICATION

2007-03-03T00:40:00.000-08:00

Verification is a huge topic and a number of books exist on the subject. As a goal of this blog, treatment of the topic has to be limited to a few aspects only.Wrong functionality which does not meet the end specification results in products which dont meet customer expectations. Hence verification of the design is needed to make sure that the end specification is met and corrective actions are

6.1. DFT (Continued)

2007-03-02T07:02:00.000-08:00

I wish to thank john (www.dftdigest.com) for his comments on my last post on DFT. BIST drives the scan chains in the design. One major advantage of BIST is that the chip can test itself and hence we can reduce or avoid time on the tester all together. Testers are costly equipment and time on the tester is expensive. Tester memory/speed determine the cost of the tester and it can run into millions

6. TESTING/ DESIGN FOR TEST

2007-02-28T07:09:00.000-08:00

I decided to cover the sub sections one by one.. First lets go with test...One major ingredient of CAD is Testing and design for Test.The thumb rule in chip design is "you can't market it until you test it". Testability has become an essential part of today's chips. Once fabricated each chip sits on a tester where functional as well as ATPG patterns are run on it to catch fabrication issues. It

Breaking down the vlsi problem into sub problems

2007-02-20T08:00:00.000-08:00

In this section we discuss some of the Major Tasks involved in the design of a SOC (System On Chip).1. Verification2. Logic Design 3. Logic synthesis and physical optimization.4. DFM (design for Manufacturability)/DFY (design for yield)5. Analog/RF (Radio Frequency), Mixed signal design.6. Testing and design for Testability.I will describe each one in a bit more detail now...1. Verification